Bibliography on Processor Frequency/Voltage Scaling
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[ABR01]
A. Acquaviva, L. Benini, and B. Riccó.
An adaptive algorithm for low-power streaming multimedia processing.
In Proceedings of the Conference on Design Automation and Test in Europe (DATE'01), 2001.
doi: 10.1109/DATE.2001.915037
[ bib | doi | .pdf ]
[ASE+04]
Alexandru Andrei, Marcus Schmitz, Petru Eles, Zebo Peng, and Bashir M. Al-Hashimi.
Overhead-conscious voltage selection for dynamic and leakage energy reduction of time-constrained systems.
In Proceedings of the Conference on Design Automation and Test in Europe (DATE'04), page 10518, Washington, DC, USA, 2004. IEEE Computer Society.
[ bib ]
[BHB+08]
Reinaldo Bergamaschi, Guoling Han, Alper Buyuktosunoglu, Hiren Patel, Indira Nair, Gero Dittmann, Geert Janssen, Nagu Dhanwada, Zhigang Hu, Pradip Bose, and John Darringer.
Exploring power management in multi-core systems.
In Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC'08), pages 708–713, Los Alamitos, CA, USA, 2008. IEEE Computer Society Press.
[ bib ]
[BR03]
B. Brock and K. Rajamani.
Dynamic power management for embedded systems.
In Proceedings of the IEEE Int'l SOC Conference (SOCC 2003), September 2003.
[ bib | .pdf ]
[CC04]
Youngjin Cho and Naehyuck Chang.
Memory-aware energy-optimal frequency assignment for dynamic supply voltage scaling.
In Proceedings of the 2004 International Symposium on Low-Power Electronics and Design (ISLPED'04), pages 387–392, New York, NY, USA, August 2004. ACM Press.
doi: 10.1145/1013235.1013327
[ bib | doi ]
[CGM+07]
P. Chaparro, J. Gonzalez, G. Magklis, Cai Qiong, and A. Gonzalez.
Understanding the thermal implications of multi-core architectures.
Parallel and Distributed Systems, IEEE Transactions on, 18(8):1055–1065, August 2007.
doi: 10.1109/TPDS.2007.1092
[ bib | doi ]
[CKC07]
Youngjin Cho, Younghyun Kim, and Naehyuck Chang.
PVS: Passive voltage scaling for wireless sensor networks.
In Proceedings of the 2007 International Symposium on Low-Power Electronics and Design (ISLPED'07), pages 135–140, New York, NY, USA, 2007. ACM.
doi: 10.1145/1283780.1283810
[ bib | doi ]
[CMSB+08]
Matthew Curtis-Maury, Ankur Shah, Filip Blagojevic, Dimitrios S. Nikolopoulos, Bronis R. de Supinski, and Martin Schulz.
Prediction models for multi-dimensional power-performance optimization on many cores.
In Proceedings of the Seventeenth Conference on Parallel Architectures and Compilation Techniques (PACT'08), pages 250–259, New York, NY, USA, 2008. ACM.
doi: 10.1145/1454115.1454151
[ bib | doi ]
[Cor04]
Intel Corporation.
Wireless Intel SpeedStep© power manager.
Technical report, Intel Corporation, 2004.
[ bib | .html ]
[CSP04a]
Kihwan Choi, Ramakrishna Soma, and Massoud Pedram.
Dynamic voltage and frequency scaling based on workload decomposition.
In Proceedings of the 2004 International Symposium on Low-Power Electronics and Design (ISLPED'04), August 2004.
doi: 10.1145/1013235.1013282
[ bib | doi | .pdf ]
[CSP04b]
Kihwan Choi, Ramakrishna Soma, and Massoud Pedram.
Fine-grained dynamic voltage and frequency scaling for precise energy and performance trade-off based on the ratio of off-chip access to on-chip computation times.
In Proceedings of the Conference on Design Automation and Test in Europe (DATE'04), February 2004.
doi: 10.1109/DATE.2004.1268819
[ bib | doi ]
[DR07]
Gaurav Dhiman and Tajana Simunic Rosing.
Dynamic voltage frequency scaling for multi-tasking systems using online learning.
In Proceedings of the 2007 International Symposium on Low-Power Electronics and Design (ISLPED'07), pages 207–212, New York, NY, USA, 2007. ACM.
doi: 10.1145/1283780.1283825
[ bib | doi ]
[FEL02]
Xiaobo Fan, Carla S. Ellis, and Alvin R. Lebeck.
Synergy between power-aware memory systems and processor voltage scaling.
Technical Report CS-2002-12, Duke University, Department of Computer Science, November 2002.
[ bib | .pdf ]
[FEL03]
Xiaobo Fan, Carla Ellis, and Alvin Lebeck.
Interactions of power-aware memory systems and processor voltage scaling.
In Proceedings of the Workshop on Power-Aware Computer Systems (PACS'03), December 2003.
[ bib | .pdf ]
[Fle01]
Marc Fleischmann.
Longrun power management.
White Paper of Transmeta Corporation, January 2001.
[ bib | .pdf ]
[FM02]
Krisztián Flautner and Trevor Mudge.
Vertigo: Automatic performance-setting for linux.
In Proceedings of the Fifth Symposium on Operating System Design and Implementation (OSDI'02), December 2002.
[ bib | .pdf ]
[FPL+07]
Vincent W. Freeh, Feng Pan, David K. Lowenthal, Nandini Kappiah, Rob Springer, Barry L. Rountree, and Mark E. Femal.
Analyzing the energy-time tradeoff in high-performance computing applications.
IEEE Transactions on Parallel and Distributed Systems, 18(6):835–848, June 2007.
[ bib | .pdf ]
[FRM01]
Krisztián Flautner, Steven Reinhardt, and Trevor Mudge.
Automatic performance setting for dynamic voltage scaling.
In Proceedings of the Seventh Annual International Conference on Mobile Computing and Networking (MOBICOM'01), July 2001.
doi: 10.1145/381677.381702
[ bib | doi ]
[FURM00]
Krisztián Flautner, Richard Uhlig, Steven K. Reinhardt, and Trevor N. Mudge.
Thread level parallelism and interactive performance of desktop applications.
In Proceedings of the Ninth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS'00), pages 129–138, 2000.
[ bib | .pdf ]
[GCW95]
K. Govil, E. Chan, and H. Wassermann.
Comparing algorithms for dynamic speed-setting of a low-power CPU.
In Proceedings of the First Annual International Conference on Mobile Computing and Networking (MOBICOM'95), March 1995.
doi: 10.1145/215530.215546
[ bib | doi ]
[GK05]
Selim Gurun and Chandra Krintz.
AutoDVS: an automatic, general-purpose, dynamic clock scheduling system for hand-held devices.
In Proceedings of the Fifth ACM International Conference on Embedded Software (EMSOFT'05), pages 218–226, September 2005.
doi: 10.1145/1086228.1086270
[ bib | doi ]
[GLM+00]
Dirk Grunwald, Philip Levis, Charles B. Morrey, Michael Neufeld, and Keith I. Farkas.
Policies for dynamic clock scheduling.
In Proceedings of the Fourth Symposium on Operating System Design and Implementation (OSDI'00), October 2000.
[ bib | .pdf ]
[GLS93]
Christos J. Georgiou, Thor A. Larsen, and Eugen Schenfeld.
Variable chip-clocking mechanism.
United States Patent 5,189,314, February 1993.
[ bib | .html ]
[HF04]
Chung-Hsing Hsu and Wu-Chun Feng.
Effective dynamic voltage scaling through CPU-boundedness detection.
In Proceedings of the Workshop on Power-Aware Computer Systems (PACS'04), December 2004.
[ bib | .pdf ]
[HF05]
Chung-hsing Hsu and Wu-chun Feng.
A power-aware run-time system for high-performance computing.
In Proceedings of the ACM/IEEE Conference on Supercomputing (SC'05), Washington, DC, USA, 2005. IEEE Computer Society.
doi: 10.1109/SC.2005.3
[ bib | doi ]
[HKQ+98]
I. Hong, D. Kirovski, G. Qu, M. Potkonjak, and M. Srivastava.
Power optimization of variable voltage core-based systems.
In Proceedings of the 35th Design Automation Conference (DAC'98), June 1998.
[ bib | .pdf ]
[HM07]
Sebastian Herbert and Diana Marculescu.
Analysis of dynamic voltage/frequency scaling in chip-multiprocessors.
In Proceedings of the 2007 International Symposium on Low-Power Electronics and Design (ISLPED'07), pages 38–43, New York, NY, USA, 2007. ACM.
doi: 10.1145/1283780.1283790
[ bib | doi ]
[HPS98]
I. Hong, M. Potkonjak, and M. Srivastava.
On-line scheduling of hard real-time tasks on variable voltage voltage processor.
In Proceedings of the International Conference on Computer-Aided Design (ICCAD'98), November 1998.
[ bib | .pdf ]
[HQPS98]
I. Hong, G. Qu, M. Potkonjak, and M. Srivastava.
Synthesis techniques for low-power hard real-time systems on variable voltage processors.
In Proceedings of the Nineteenth Real-Time Systems Symposium (RTSS'98), December 1998.
doi: 10.1109/REAL.1998.739744
[ bib | doi ]
[IBC+06]
Canturk Isci, Alper Buyuktosunoglu, Chen-Yong Cher, Pradip Bose, and Margaret Martonosi.
An analysis of efficient multi-core global power management policies: Maximizing performance for a given power budget.
In Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture (MIRCO'06), pages 347–358, Washington, DC, USA, 2006. IEEE Computer Society.
doi: 10.1109/MICRO.2006.8
[ bib | doi ]
[ICM06]
Canturk Isci, Gilberto Contreras, and Margaret Martonosi.
Live, runtime phase monitoring and prediction on real systems with application to dynamic power management.
In Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture (MIRCO'06), pages 359–370, Washington, DC, USA, 2006. IEEE Computer Society.
doi: 10.1109/MICRO.2006.30
[ bib | doi | .pdf ]
[IMB05]
Canturk Isci, Margaret Martonosi, and Alper Buyuktosunoglu.
Long-term workload phases: Duration predictions and applications applications to DVFS.
IEEE Micro, 25(5):39–51, September 2005.
doi: 10.1109/MM.2005.93
[ bib | doi ]
[Int99]
Intel.
Intel StrongARM SA-1100 Microprocessor Developer's Manual, April 1999.
[ bib ]
[Int00a]
Intel.
Intel SpeedStep Technology, January 2000.
[ bib | .html ]
[Int00b]
Intel.
Intel XScale Microarchitecture Technical Summary, July 2000.
[ bib | .pdf ]
[Int01]
Intel.
Intel® IQ80310 Evaluation Platform, July 2001.
[ bib ]
[Int03]
Intel.
Intel® 80200 Processor based on Intel® XScale Microarchitecture Developer's Manual, March 2003.
[ bib ]
[JG04]
Ravindra Jejurikar and Rajesh Gupta.
Dynamic voltage scaling for systemwide energy minimization in real-time embedded systems.
In Proceedings of the 2004 International Symposium on Low-Power Electronics and Design (ISLPED'04), pages 78–81, New York, NY, USA, August 2004. ACM Press.
doi: 10.1145/1013235.1013261
[ bib | doi ]
[Jha01]
Niraj K. Jha.
Low power system scheduling and synthesis.
In Proceedings of the International Conference on Computer-Aided Design (ICCAD'01), pages 259–263, Piscataway, NJ, USA, 2001. IEEE Press.
[ bib ]
[JWP+05]
Philo Juang, Qiang Wu, Li-Shiuan Peh, Margaret Martonosi, and Douglas W. Clark.
Coordinated, distributed, formal energy management of chip multiprocessors.
In Proceedings of the 2005 International Symposium on Low-Power Electronics and Design (ISLPED'05), pages 127–130, New York, NY, USA, August 2005. ACM Press.
doi: 10.1145/1077603.1077637
[ bib | doi ]
[KF09]
Viren Kumar and Alexandra Fedorova.
Towards better performance per watt in virtual environments on asymmetric single-ISA multi-core systems.
SIGOPS Operating Systems Review, 43(3):105–109, 2009.
doi: 10.1145/1618525.1618538
[ bib | doi ]
[KGKR05]
Ramakrishna Kotla, Soraya Ghiasi, Tom Keller, and Freeman Rawson.
Scheduling processor voltage and frequency in server and cluster systems.
In Proceedings of the Nineteenth IEEE International Parallel and Distributed Processing Symposium (IPDPS'05), page 234.2, Washington, DC, USA, 2005. IEEE Computer Society.
doi: 10.1109/IPDPS.2005.392
[ bib | doi ]
[KKM04]
Woonseok Kim, Jihong Kim, and Sang Lyul Min.
Preemption-aware dynamic voltage scaling in hard real-time systems.
In Proceedings of the 2004 International Symposium on Low-Power Electronics and Design (ISLPED'04), pages 393–398, New York, NY, USA, August 2004. ACM Press.
doi: 10.1145/1013235.1013328
[ bib | doi ]
[Kla00]
Alexander Klaiber.
The technology behind crusoe processors.
White Paper of Transmeta Corporation, January 2000.
[ bib | .pdf ]
[KSN07]
Masaaki Kondo, Hiroshi Sasaki, and Hiroshi Nakamura.
Improving fairness, throughput and energy-efficiency on a chip multiprocessor through dvfs.
SIGARCH Comput. Archit. News, 35(1):31–38, 2007.
doi: 10.1145/1241601.1241609
[ bib | doi ]
[LCCF08]
Wen-Yew Liang, Shih-Chang Chen, Yang-Lang Chang, and Jyh-Perng Fang.
Memory-aware dynamic voltage and frequency prediction for portable devices.
In Proceedings of the Fourteenth IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA'08), pages 229–236, August 2008.
doi: 10.1109/RTCSA.2008.19
[ bib | doi ]
[LM06]
Jian Li and Jose F. Martinez.
Dynamic power-performance adaptation of parallel computation on chip multiprocessors.
In Proceedings of the Twelfth International Symposium on High-Performance Computer Architecture (HPCA'06), pages 77–87, February 2006.
doi: 10.1109/HPCA.2006.1598114
[ bib | doi | .pdf ]
[Lor01]
Jacob Rubin Lorch.
Operating Systems Techniques for Reducing Processor Energy Consumption.
PhD thesis, Computer Science Division, University of California, Berkeley, 2001.
[ bib | .pdf ]
[LS01]
Jacob R. Lorch and Alan Jay Smith.
Improving dynamic voltage scaling algorithms with PACE.
In Proceedings of the International Conference on Measurement and Modeling of Computer Systems (SIGMETRICS'01), June 2001.
doi: 10.1145/378420.378429
[ bib | doi ]
[LS03a]
Jacob R. Lorch and Alan Jay Smith.
Operating system modifications for task-based speed and voltage scheduling.
In Proceedings of the First International Conference on Mobile Systems, Applications, and Services (MOBISYS'03), pages 215–229, May 2003.
[ bib ]
[LS03b]
Jacob R. Lorch and Alan Jay Smith.
Using user interface event information in dynamic voltage scaling algorithms.
In Proceedings of the Eleventh IEEE International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunications Systems (MASCOTS'03), October 2003.
doi: 10.1109/MASCOT.2003.1240641
[ bib | doi ]
[LS04]
Jacob R. Lorch and Alan Jay Smith.
PACE: a new approach to dynamic voltage scaling.
IEEE Transactions on Computers, 53(7):856–869, July 2004.
doi: 10.1109/TC.2004.35
[ bib | doi ]
[Mar99]
Thomas L. Martin.
Balancing Batteries, Power and Performance: System Issues in CPU Speed-Setting for Mobile Computing.
PhD thesis, Department of Electrical and Computer Engineering, Carnegie Mellon University, 1999.
[ bib | .pdf ]
[Mar00]
D. Marculescu.
On the use of microarchitecture-driven dynamic voltage scaling.
In Proceedings of the Workshop on Complexity-Effective Design, in conjunction with International Symposium on Computer Architecture (ISCA), 2000.
[ bib | .ps ]
[MB08]
Andreas Merkel and Frank Bellosa.
Memory-aware scheduling for energy efficiency on multicore processors.
In Proceedings of the Workshop on Power Aware Computing and Systems (HotPower'08), San Diego, CA, USA, December 2008.
[ bib | .pdf ]
[MFMB02]
Steven M. Martin, Krisztian Flautner, Trevor Mudge, and David Blaauw.
Combined dynamic voltage scaling and adaptive body biasing for lower power microprocessors under dynamic workloads.
In Proceedings of the International Conference on Computer-Aided Design (ICCAD'02), pages 721–725, New York, NY, USA, 2002. ACM.
doi: 10.1145/774572.774678
[ bib | doi ]
[MLH+02]
Akihiko Miyoshi, Charles Lefurgy, Eric Van Hensbergen, Ram Rajamony, and Raj Rajkumar.
Critical power slope: understanding the runtime effects of frequency scaling.
In Proceedings of the Sixteenth Annual International Conference on Supercomputing (ICS'02), pages 35–44, June 2002.
doi: 10.1145/514191.514200
[ bib | doi ]
[MMSS96]
Arif Merchant, Benjamin Melamed, Eugen Schenfeld, and Bhaskar Sengupta.
Analysis of a control mechanism for a variable speed processor.
IEEE Transactions on Computers, 45(7), July 1996.
doi: 10.1109/12.508318
[ bib | doi ]
[MPB+06]
R. McGowen, C.A. Poirier, C. Bostak, J. Ignowski, M. Millican, W.H. Parks, and S. Naffziger.
Power and temperature control on a 90-nm itanium family processor.
Solid-State Circuits, IEEE Journal of, 41(1):229–237, January 2006.
doi: 10.1109/JSSC.2005.859902
[ bib | doi ]
[MRKI07]
Konrad Malkowski, Padma Raghavan, Mahmut Kandemir, and Mary Jane Irwin.
Phase-aware adaptive hardware selection for power-efficient scientific computations.
In Proceedings of the 2007 International Symposium on Low-Power Electronics and Design (ISLPED'07), pages 403–406, New York, NY, USA, 2007. ACM.
doi: 10.1145/1283780.1283869
[ bib | doi ]
[MS99]
T. Martin and D. Siewiorek.
The impact of battery capacity and memory bandwidth on CPU speed-setting: a case study.
In Proceedings of the 1999 International Symposium on Low-Power Electronics and Design (ISLPED'99), August 1999.
[ bib | .pdf ]
[MSS+03]
Grigorios Magklis, Michael L. Scott, Greg Semeraro, David H. Albonesi, and Steven Dropsho.
Profile-based dynamic voltage and frequency scaling for a multiple clock domain microprocessor.
In Proceedings of the 30th International Symposium on Computer Architecture (ISCA'03), June 2003.
doi: 10.1145/859618.859621
[ bib | doi ]
[Muc01]
Philip Mucci.
The performance API PAPI.
White Paper of the University of Tennessee, March 2001.
[ bib | http ]
[NRM+06]
Alon Naveh, Efraim Rotem, Avi Mendelson, Simcha Gochman, Rajshree Chabukswar, Karthik Krishnan, and Arun Kumar.
Power and thermal management in the intel core duo processor.
Intel Technology Journal, 10(2), 2006.
doi: 10.1535/itj.1002.03
[ bib | doi | .pdf ]
[PB98a]
T. Pering and R. Broderson.
Dynamic voltage scaling and the design of a low-power microprocessor system.
In Proceedings of the Power Driven Microarchitecture Workshop, attached to ISCA98, June 1998.
[ bib | .html ]
[PB98b]
T. Pering and R. Broderson.
Energy efficient voltage scheduling for real-time operating systems.
In Proceedings of the 4th IEEE Real-Time Technology and Applications Symposium RTAS'98, Work in Progress Session, June 1998.
[ bib | .html ]
[PBB98]
Trevor Pering, Tom Burd, and Robert Brodersen.
The simulation and evaluation of dynamic voltage scaling algorithms.
In Proceedings of the 1998 International Symposium on Low-Power Electronics and Design (ISLPED'98), pages 76–81, New York, NY, USA, June 1998. ACM Press.
doi: 10.1145/280756.280790
[ bib | doi | .pdf ]
[PBB00]
T. Pering, T. Burd, and R. Broderson.
Voltage scheduling in the lpARM microprocessor system.
In Proceedings of the 2000 International Symposium on Low-Power Electronics and Design (ISLPED'00), July 2000.
doi: 10.1145/344166.344530
[ bib | doi ]
[PLS01a]
J. Pouwelse, K. Langendoen, and H. Sips.
Energy priority scheduling for variable voltage processors.
In Proceedings of the 2001 International Symposium on Low-Power Electronics and Design (ISLPED'01), August 2001.
doi: 10.1145/383082.383089
[ bib | doi ]
[PLS01b]
Johan Pouwelse, Koen Langendoen, and Henk Sips.
Dynamic voltage scaling on a low-power microprocessor.
In Proceedings of the Seventh Annual International Conference on Mobile Computing and Networking (MOBICOM'01), July 2001.
doi: 10.1145/381677.381701
[ bib | doi ]
[PLS03]
J. Pouwelse, K. Langendoen, and H. Sips.
Application-directed voltage scaling.
IEEE Transactions on Very Large Scale Integration (TVLSI), 11(5):812–826, October 2003.
doi: 10.1109/TVLSI.2003.814324
[ bib | doi ]
[PS01]
P. Pillai and K. Shin.
Real-time dynamic voltage scaling for low-power embedded operating systems.
In Proceedings of the Eighteenth Symposium on Operating System Principles (SOSP'01), October 2001.
[ bib | .pdf ]
[PSS05]
Christian Poellabauer, Leo Singleton, and Karsten Schwan.
Feedback-based dynamic frequency scaling for memory-bound real-time applications.
In Proceedings of the Eleventh Real-Time and Embedded Technology and Applications Symposium (RTAS'05), March 2005.
[ bib | .pdf ]
[PZPS05]
Christian Poellabauer, Tao Zhang, Santosh Pande, and Karsten Schwan.
An efficient frequency scaling approach for energy-aware embedded real-time systems.
In Proceedings of the International Conference on Architecture of Computing Systems (ARCS'05), March 2005.
[ bib | .pdf ]
[RABB05]
Martino Ruggiero, Andrea Acquaviva, Davide Bertozzi, and Luca Benini.
Application-specific power-aware workload allocation for voltage scalable MPSoC platforms.
In Proceedings of the 2005 International Conference on Computer Design (ICCD'05), October 2005.
doi: 10.1109/ICCD.2005.24
[ bib | doi ]
[RFS+06]
Cosmin Rusu, Alexandre Ferreira, Claudio Scordino, Aaron Watson, Rami Melhem, and Daniel Mosse.
Energy-efficient real-time heterogeneous server clusters.
In Proceedings of the Twelfth Real-Time and Embedded Technology and Applications Symposium (RTAS'06), April 2006.
[ bib | .pdf ]
[RMDM07]
Tajana Simunic Rosing, Kresimir Mihic, and Giovanni De Micheli.
Power and reliability management of SoCs.
IEEE Transactions on Very Large Scale Integrated Systems, 15(4):391–403, 2007.
doi: 10.1109/TVLSI.2007.895245
[ bib | doi ]
[RMNM04]
Efi Rotem, Avi Mendelson, Alon Naveh, and Micha Moffie.
Analysis of the enhanced intel speedstep technology of the pentium m processor.
In Proceedings of the First Workshop on Temperature-Aware Computer Systems (TACS'04), June 2004.
[ bib | .pdf ]
[RPSG05]
Vijay Raghunathan, Cristiano L. Pereira, Mani B. Srivastava, and Rajesh K. Gupta.
Energy aware wireless systems with adaptive power-fidelity tradeoffs.
IEEE Transactions on Very Large Scale Integration (TVLSI), 13(2):211–225, February 2005.
doi: 10.1109/TVLSI.2004.840773
[ bib | doi ]
[RVC02]
Daler Rakhmatov, Sarma Vrudhula, and Chaitali Chakrabarti.
Battery-conscious task sequencing for portable devices including voltage/clock scaling.
In Proceedings of the 39th Design Automation Conference (DAC'02), June 2002.
doi: 10.1145/513918.513967
[ bib | doi ]
[RWB09]
Krishna K. Rangan, Gu-Yeon Wei, and David Brooks.
Thread motion: fine-grained power management for multi-core systems.
In Proceedings of the 36th International Symposium on Computer Architecture (ISCA'09), pages 302–313, New York, NY, USA, June 2009. ACM.
doi: 10.1145/1555754.1555793
[ bib | doi ]
[SAMR03]
Kiran Seth, Aravindh Anantaraman, Frank Mueller, and Eric Rotenberg.
Fast: Frequency-aware static timing analysis.
In Proceedings of the 24th Real-Time Systems Symposium (RTSS'03), page 40, Los Alamitos, CA, USA, 2003. IEEE Computer Society.
doi: 10.1109/REAL.2003.1253252
[ bib | doi ]
[SBA+01]
Tajana Simunic, Luca Benini, Andrea Acquaviva, Peter Glynn, and Giovanni De Micheli.
Dynamic voltage scaling and power management for portable systems.
In Proceedings of the 38th Design Automation Conference (DAC'01), 2001.
[ bib | .pdf ]
[SBB07]
Joseph Sharkey, Alper Buyuktosunoglu, and Pradip Bose.
Evaluating design tradeoffs in on-chip power management for CMPs.
In Proceedings of the 2007 International Symposium on Low-Power Electronics and Design (ISLPED'07), pages 44–49, New York, NY, USA, 2007. ACM.
doi: 10.1145/1283780.1283791
[ bib | doi ]
[SBG01]
Shmuel Shaffer, William J. Beyda, and Cheryl Gold.
Apparatus and method for automatic cpu speed control based on application-specific criteria.
United States Patent 6,298,448, October 2001.
[ bib | .html ]
[SLSPH09]
David C. Snowdon, Etienne Le Sueur, Stefan M. Petters, and Gernot Heiser.
Koala: a platform for OS-level power management.
In Fourth ACM SIGOPS EuroSys Conference, pages 289–302, New York, NY, USA, 2009. ACM.
doi: 10.1145/1519065.1519097
[ bib | doi ]
[SMB+02]
Greg Semeraro, Grigorios Magklis, Rajeev Balasubramonian, David H. Albonesi, Sandhya Dwarkadas, and Michael L. Scott.
Energy-efficient processor design using multiple clock domains with dynamic voltage and frequency scaling.
In Proceedings of the Eighth International Symposium on High-Performance Computer Architecture (HPCA'02), February 2002.
doi: 10.1109/HPCA.2002.995696
[ bib | doi ]
[SMHK02]
P. Stanley-Marbell, M. Hsiao, and U. Kremer.
A hardware architecture for dynamic performance and energy adaption.
In Proceedings of the Workshop on Power-Aware Computer Systems (PACS'02), February 2002.
[ bib | .ps ]
[SPH07]
David C. Snowdon, Stefan M. Petters, and Gernot Heiser.
Accurate on-line prediction of processor and memory energy usage under voltage scaling.
In Proceedings of the Seventh ACM International Conference on Embedded Software (EMSOFT'07), pages 84–93, New York, NY, USA, 2007. ACM.
doi: 10.1145/1289927.1289945
[ bib | doi | .pdf ]
[SRH05]
David C. Snowdon, Sergio Ruocco, and Gernot Heiser.
Power management and dynamic voltage scaling: Myths and facts.
In Proceedings of the 2005 Workshop on Power Aware Real-time Computing, September 2005.
[ bib | .pdf ]
[SvdLPH07]
David C. Snowdon, Godfrey van der Linden, Stefan M. Petters, and Gernot Heiser.
Accurate run-time prediction of performance degradation under frequency scaling.
In 3rd Workshop on Operating System Platforms for Embedded Real-Time Applications, July 2007.
[ bib | .pdf ]
[TT08]
Radu Teodorescu and Josep Torrellas.
Variation-aware application scheduling and power management for chip multiprocessors.
In Proceedings of the 35th International Symposium on Computer Architecture (ISCA'08), pages 363–374, Washington, DC, USA, 2008. IEEE Computer Society.
doi: 10.1109/ISCA.2008.40
[ bib | doi | .pdf ]
[UU04a]
Sascha Uhrig and Theo Ungerer.
Fine-grained power management for multithreaded processor cores.
In Proceedings of the ACM Symposium on Applied Computing (SAC'04), pages 907–908, March 2004.
doi: 10.1145/967900.968083
[ bib | doi ]
[UU04b]
Sascha Uhrig and Theo Ungerer.
Fine-grained power management for real-time embedded processors.
In Proceedings of RTS Embedded Systems 2004, March 2004.
[ bib | .pdf ]
[VGS+03]
A. Varma, B. Ganesh, M. Sen, S. R. Choudhary, L. Srinivasan, and B. Jacob.
A control-theoretic approach to dynamic voltage scaling.
In Proceedings of the International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES'03), October 2003.
[ bib | .pdf ]
[VM03]
Girish Varatkar and Radu Marculescu.
Communication-aware task scheduling and voltage selection for total systems energy minimization.
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