Memory Access - The Third Dimension of Scheduling

Memory Access - The Third Dimension of Scheduling

Frank Bellosa

english Jan. 1997, 8 pages

TR-I4-97-01

[Abstract] [Full Paper (ps,http) , 43 kB] [Full Paper (pdf) , 24 kB]

Abstract: Up to now, two internal events influence scheduling decisions of contemporary operating systems: timer events and I/O-related interrupts. Timing information supports preemption and priority adjustment. Knowledge about  issued or  completed I/O operations helps to wake-up sleeping processes and to boost their priority. Preferring deblocked processes at the end of I/O operations improves the interactive performance and saves buffer space because available data is consumed short after its availability. With the upcoming of processors clocked with hundreds of megahertz, the processor speed exceeds the speed of affordable memory by factors. If it is accepted to influence execution priorities by slow I/O events, why should scheduling neglect events related to other slow devices like main memory and memory data paths? Our novel approach to scheduling is based on knowledge derived from counters in the memory subsystem. We demonstrate that the usage of information related to cache- and main-memory access opens new dimensions in real-time and time-slice scheduling of shared-memory architectures. Advanced cache-affinity scheduling, memory-bandwidth guarantees for real-time jobs, and new processor assignment strategies are three basic concepts of a new scheduling philosophy focusing more on memory access than on CPU cycles as the performance determinant factor.