Last change: 23.3.1995

Hardware DSM Implementations

The MIT Alewife project implements a large-scale multiprocessor that integrates both cache-coherent, distributed shared memory and user-level message-passing in a single integrated hardware framework. Each Alewife node consists of a 33 MHz Sparcle integer unit, an off-the-shelf FPU, 64 kbytes of direct-mapped cache, and 4 Mbytes of globally-shared main memory. The nodes communicate via messages on a two-dimensional mesh network. The current implementation scales directly to 512 nodes.

All publications about MIT Alewife are available here.

The Wisconsin Wind Tunnel (WWT) Project seeks to develop a consensus about the middle-level interface--below languages and compilers and above system software and hardware. Our first proposed interface was Cooperative Shared Memory, which is an evolutionary extension to conventional shared-memory software and hardware. Recently, we have been working on a more revolutionary interface called Tempest. Tempest provides the mechanisms that allow programmers, compilers, and program libraries to implement and use message passing, transparent shared memory, and hybrid combinations of the two.

Here is a Link to the complete technical papers about WWT.

The Stanford FLASH (Flexible Architecture for SHared memory) multiprocessor will be a scalable multiprocessorable to support a variety of communication models, including shared memory and message passing protocols, through the use of a programmable node controller. We plan to provide the architectural support necessary to use FLASH as a traditional "standalone" supercomputer, a compute server, a robust multiuser system, or a distributed system.

FLASH publications are available.

It's predecessor, the DASH machine, was also developed at Stanford. Papers about DASH can be found at the FLASH publication location. A paper describing the DASH hardware design and performance evaluation is

Daniel Lenoski, James Laudon, Truman Joe, David Nakahira, Luis Stevens, Anoop Gupta, and John Hennessy, "The DASH Prototype: Implementation and Performance".

A report on various memory consistency models evaluated for use in DASH is Kourosh Gharachorloo, Anoop Gupta, and John Hennessy, "Performance Evaluation of Memory Consistency Models for Shared Memory Multiprocessors".

The Convex Company works heavily on building a commercial Scalable Parallel Processing (SPP) architecture. They provide a Global Shared Memory abstraction onto a massive parallel processor machine.

Erich Meier, Uni Erlangen, 1995