
Access to Control Register of a CPU core. More...
Classes | |
class | Core::CR< id > |
Access to the Control Register. More... | |
Namespaces | |
Core | |
Implements an abstraction for CPU internals. | |
Enumerations | |
enum | Core::CR0 { Core::CR0_PE = 1 << 0, Core::CR0_MP = 1 << 1, Core::CR0_EM = 1 << 2, Core::CR0_TS = 1 << 3, Core::CR0_ET = 1 << 4, Core::CR0_NE = 1 << 15, Core::CR0_WP = 1 << 16, Core::CR0_AM = 1 << 18, Core::CR0_NW = 1 << 29, Core::CR0_CD = 1 << 30, Core::CR0_PG = 1 << 31 } |
Control Register 0. More... | |
enum | Core::CR4 { Core::CR4_VME = 1 << 0, Core::CR4_PVI = 1 << 1, Core::CR4_TSD = 1 << 2, Core::CR4_DE = 1 << 3, Core::CR4_PSE = 1 << 4, Core::CR4_PAE = 1 << 5, Core::CR4_MCE = 1 << 6, Core::CR4_PGE = 1 << 7, Core::CR4_PCE = 1 << 8, Core::CR4_OSFXSR = 1 << 9, Core::CR4_OSXMMEXCPT = 1 << 10, Core::CR4_UMIP = 1 << 11, Core::CR4_VMXE = 1 << 13, Core::CR4_SMXE = 1 << 14, Core::CR4_FSGSBASE = 1 << 16, Core::CR4_PCIDE = 1 << 17, Core::CR4_OSXSAVE = 1 << 18, Core::CR4_SMEP = 1 << 20, Core::CR4_SMAP = 1 << 21, Core::CR4_PKE = 1 << 22 } |
Control Register 4. More... | |
Access to Control Register of a CPU core.