LAPIC::IPI Namespace Reference

Inter-Processor Interrupts. More...

Classes
union	InterruptCommand
	Interrupt Command. More...
struct	InterruptCommand.__unnamed__

Enumerations
enum	DeliveryMode {   FIXED = 0, LOWEST_PRIORITY = 1, SMI = 2, NMI = 4,   INIT = 5, INIT_LEVEL_DEASSERT = 5, STARTUP = 6 }
	Delivery mode specifies the type of interrupt sent to the CPU. More...
enum	DestinationMode { PHYSICAL = 0, LOGICAL = 1 }
	Way of interpreting the value written to the destination field. More...
enum	DeliveryStatus { IDLE = 0, SEND_PENDING = 1 }
	Interrupt state. More...
enum	Level { DEASSERT = 0, ASSERT = 1 }
	Interrupt level. More...
enum	TriggerMode { EDGE_TRIGGERED = 0, LEVEL_TRIGGERED = 1 }
	Trigger mode for DeliveryMode::INIT_LEVEL_DEASSERT. More...
enum	DestinationShorthand { NO_SHORTHAND = 0, SELF = 1, ALL_INCLUDING_SELF = 2, ALL_EXCLUDING_SELF = 3 }
	Shorthand for commonly used destinations. More...
enum	InterruptMask { UNMASKED = 0, MASKED = 1 }
	Interrupt mask. More...

Functions
bool	isDelivered ()
	Check if the previously sent IPI has reached its destination. More...
void	send (uint8_t destination, uint8_t vector)
	Send an Inter-Processor Interrupt (IPI) More...
void	sendGroup (uint8_t logical_destination, uint8_t vector)
	Send an Inter-Processor Interrupt (IPI) to a group of processors. More...
void	sendAll (uint8_t vector)
	Send an Inter-Processor Interrupt (IPI) to all processors (including self) More...
void	sendOthers (uint8_t vector)
	Send an Inter-Processor Interrupt (IPI) to all other processors (all but self) More...
void	sendInit (bool assert=true)
void	sendStartup (uint8_t vector)

Detailed Description

Inter-Processor Interrupts.

For multi-core systems, the LAPIC enables sending messages (Inter-Processor Interrupts, IPIs) to other CPU cores and receiving those sent from other cores.

See also

ISDMv3 10.6 Issuing Interprocessor Interrupts

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Class Documentation

LAPIC::IPI::InterruptCommand.__unnamed__

struct LAPIC::IPI::InterruptCommand.__unnamed__

Class Members
uint64_t	vector: 8	Interrupt vector in the Interrupt Descriptor Table (IDT) will be activated when the corresponding external interrupt triggers. Interrupt vector in the Interrupt Descriptor Table (IDT) will be activated when the corresponding external interrupt triggers.
enum DeliveryMode	delivery_mode: 3	The delivery mode denotes the way the interrupts will be delivered to the local CPU cores, respectively to their local APICs. For StuBS, we use DeliveryMode::LowestPriority, as all CPU cores have the same priority and we want to distribute interrupts evenly among them. It, however, is not guaranteed that this method of load balancing will work on every system.
enum DestinationMode	destination_mode: 1	The destination mode defines how the value stored in destination will be interpreted. For StuBS, we use DestinationMode::Logical.
enum DeliveryStatus	delivery_status: 1	Delivery status holds the current status of interrupt delivery. Note This field is read only; write accesses to this field will be ignored.
uint64_t	__pad0__: 1	reserved
enum Level	level: 1	The polarity denotes when an interrupt should be issued. For StuBS, we use Polarity::High (i.e., when the interrupt line is, logically, 1).
enum TriggerMode	trigger_mode: 1	The trigger mode states whether the interrupt signaling is level or edge triggered. StuBS uses TriggerMode::Edge for Keyboard and Timer, the (optional) serial interface, however, needs TriggerMode::Level.
uint64_t	__pad1__: 2	reserved
enum DestinationShorthand	destination_shorthand: 2
uint64_t	__pad2__: 36	Reserved, do not modify.
uint64_t	destination: 8	Interrupt destination. The meaning of destination depends on the destination mode: For the logical destination mode, destination holds a bit mask made up of the cores that are candidates for receiving the interrupt. In the single-core case, this value is 1, in the multi-core case, the n low-order bits needs to be set (with n being the number of CPU cores, see Core::count() ). Setting the n low-order bits marks all available cores as candidates for receiving interrupts and thereby balancing the number of interrupts between the cores. Note This form of load balancing depends on the hardware's behavior and may not work on all systems in the same fashion. Most notably, in QEMU all interrupts are sent to the BSP (core 0).

Enumeration Type Documentation

DeliveryMode

enum LAPIC::IPI::DeliveryMode

Delivery mode specifies the type of interrupt sent to the CPU.

Enumerator
FIXED	"ordinary" interrupt; send to ALL cores listed in the destination bit mask
LOWEST_PRIORITY	"ordinary" interrupt; send to the lowest priority core from destination mask
SMI	System Management Interrupt; vector number required to be 0.
NMI	Non-Maskable Interrupt, vector number ignored, only edge triggered.
INIT	Initialization interrupt (always treated as edge triggered)
INIT_LEVEL_DEASSERT	Synchronization interrupt.
STARTUP	Dedicated Startup-Interrupt (SIPI)

DestinationMode

enum LAPIC::IPI::DestinationMode

Way of interpreting the value written to the destination field.

Enumerator
PHYSICAL	Destination contains the physical destination APIC ID.
LOGICAL	Destination contains a mask of logical APIC IDs.

DeliveryStatus

enum LAPIC::IPI::DeliveryStatus

Interrupt state.

Enumerator
IDLE	No activity for this interrupt.
SEND_PENDING	Interrupt will be sent as soon as the bus / LAPIC is ready.

Level

enum LAPIC::IPI::Level

Interrupt level.

Enumerator
DEASSERT	Must be zero when DeliveryMode::INIT_LEVEL_DEASSERT.
ASSERT	Must be one for all other delivery modes.

TriggerMode

enum LAPIC::IPI::TriggerMode

Trigger mode for DeliveryMode::INIT_LEVEL_DEASSERT.

Enumerator
EDGE_TRIGGERED	edge triggered
LEVEL_TRIGGERED	level triggered

DestinationShorthand

enum LAPIC::IPI::DestinationShorthand

Shorthand for commonly used destinations.

Enumerator
NO_SHORTHAND	Use destination field instead of shorthand.
SELF	Send IPI to self.
ALL_INCLUDING_SELF	Send IPI to all including self.
ALL_EXCLUDING_SELF	Send IPI to all except self.

InterruptMask

enum LAPIC::IPI::InterruptMask

Interrupt mask.

Enumerator
UNMASKED	Interrupt entry is active (non-masked)
MASKED	Interrupt entry is deactivated (masked)

Function Documentation

isDelivered()

bool LAPIC::IPI::isDelivered

(

)

Check if the previously sent IPI has reached its destination.

Returns

true if the previous IPI was accepted from its target processor, otherwise false

send()

void LAPIC::IPI::send	(	uint8_t	destination,
		uint8_t	vector
	)

Send an Inter-Processor Interrupt (IPI)

Parameters

destination	ID of the target processor (use APIC::getLAPICID(core) )
vector	Interrupt vector number to be triggered

sendGroup()

void LAPIC::IPI::sendGroup	(	uint8_t	logical_destination,
		uint8_t	vector
	)

Send an Inter-Processor Interrupt (IPI) to a group of processors.

Parameters

logical_destination	Mask containing the logical APIC IDs of the target processors (use APIC::getLogicalLAPICID())
vector	Interrupt vector number to be triggered

sendAll()

void LAPIC::IPI::sendAll

(

uint8_t

vector

)

Send an Inter-Processor Interrupt (IPI) to all processors (including self)

Parameters

vector

Interrupt vector number to be triggered

sendOthers()

void LAPIC::IPI::sendOthers

(

uint8_t

vector

)

Send an Inter-Processor Interrupt (IPI) to all other processors (all but self)

Parameters

vector

Interrupt vector number to be triggered