Class abstracting a single HPET comparator. More...
#include <machine/hpet.h>
Classes | |
| union | ConfigAndCapabilitiesRegister |
| Access Helper for comparators configuration register. More... | |
| struct | ConfigAndCapabilitiesRegister.__unnamed__ |
Public Member Functions | |
| Comparator (const Comparator &)=delete | |
| Comparator (Comparator &&)=delete | |
| Comparator & | operator= (const Comparator &)=delete |
| Comparator & | operator= (Comparator &&)=delete |
| void | enable () |
| Activates interrupts (for the current comparator). | |
| void | disable () |
| Deactivates interrupts (for the current comparator). | |
| bool | isEnabled () const |
| Checks whether interrupts are enabled for the current comparator. | |
| bool | supportsIOAPICSlot (unsigned slot) const |
| Can this comparator trigger interrupts at an specific I/O-APIC Slot? More... | |
| bool | supportsPeriodicInterrupts () const |
| Is this comparator capable of sending peridic interrupts? More... | |
| bool | isActive () const |
| Check if this comparator triggered an interrupt. More... | |
| void | setHandled () |
| Mark this comparator interrupt as handled. More... | |
| bool | set (uint64_t usecs, uint8_t slot, bool periodic) |
| Sets the comperator. More... | |
Protected Types | |
| enum | TriggerMode { EDGE = 0, LEVEL = 1 } |
| Trigger mode for the interrupts generated by a comparator. More... | |
| enum | ComparatorMode { ONE_SHOT = 0, PERIODIC = 1 } |
| Comparator mode a comparator is running in. More... | |
Protected Attributes | |
| volatile uint64_t | config_register |
| Comparator Configuration and Capability Register. More... | |
| volatile uint64_t | value_register |
| Comparator Value Register. More... | |
| volatile uint64_t | fsb_register |
| Comparator FSB Interrupt Route Register. More... | |
Class abstracting a single HPET comparator.
Abstracts the access to comparators. This class does not have any constructor, as it is used to encapsulate hardware structures already residing in memory.
The Registers for HPET comparator n are memory mapped at HPET base address plus offset
i4stubs-all@lists.cs.fau.de0x100 + 0x20 * n for Configuration and Capability Register0x108 + 0x20 * n for Comparator Value Register and0x110 + 0x20 * n for FSB Interrupt Route RegisterUse HPET::getComparator to obtain an instance for a particular HPET comparator.
| struct HPET::Comparator::ConfigAndCapabilitiesRegister.__unnamed__ |
| Class Members | ||
|---|---|---|
| uint64_t | __pad0__: 1 | |
| TriggerMode | trigger_mode: 1 | Generate edge or level triggered interrupts. |
| uint64_t | interrupt_status: 1 |
Enable (1) or disable (0) interrupts. |
| ComparatorMode | comparator_mode: 1 | periodic or one shot mode |
| uint64_t | periodic_capable: 1 | Is timer capable of periodic mode (read-only) |
| CounterSize | counter_size: 1 | 32- or 64bit size (read-only) |
| uint64_t | set_value: 1 | if set to 1, the accumulator can be set in software |
| uint64_t | __pad1__: 1 | |
| uint64_t | small_mode: 1 | if set to 1 while supporting 64bit size, the timer runs in 32-bit mode |
| uint64_t | ioapic_slot: 5 |
I/O-APIC slot (must be set in mask supported_ioapic_slots) |
| uint64_t | fsb_interrupt_enabled: 1 | if set to 1, the timer will use FSB interrupt mapping |
| uint64_t | fsb_interrupt_delivery: 1 | if set to 1, the timer supports FSB interrupt mapping (read-only) |
| uint64_t | __pad2__: 16 | |
| uint64_t | supported_ioapic_slots: 32 | bit mask containing the supported I/O APIC slots (read-only) |
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protected |
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Can this comparator trigger interrupts at an specific I/O-APIC Slot?
The standard mapping (not legacy or FSB!) is able to route interrupts to some I/O APIC slots. The possible slots can be determined by the corresponding bit in supported_ioapic_slots of the ConfigAndCapabilitiesRegister
| slot | I/O-APIC slot to check |
true if comparator is capable to route interrupts to the given slot
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inline |
Is this comparator capable of sending peridic interrupts?
true if comparator is capable of periodic interrupts | bool HPET::Comparator::isActive | ( | ) | const |
Check if this comparator triggered an interrupt.
Reads the corresponding bit of the General Interrupt Status Register if this comparator triggered an interrupt
| void HPET::Comparator::setHandled | ( | ) |
Mark this comparator interrupt as handled.
Sets the corresponding bit of the General Interrupt Status Register to mark the interrupt of this comparator as handled.
| bool HPET::Comparator::set | ( | uint64_t | usecs, |
| uint8_t | slot, | ||
| bool | periodic | ||
| ) |
Sets the comperator.
Calculates the required ticks, sets the mode and I/O APIC slot for this comparator.
Since the I/O APIC slot might be shared with another device, the comparator should be configured to use level triggered interrupts (in standard interrupt mapping). The handler has to use isActive to verify that this HPET comparator was the source and mark it as handled.
| usecs | time to wait in micro seconds. |
| slot | I/O APIC slot to be triggered on expiry of waiting time |
| periodic | If set, the interrupt will be issued periodically |
true iff comperator was set up successful, false otherwise.
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Comparator Configuration and Capability Register.
In addition to global configuration and value registers, every HPET comparator comes with its own configuration register containing config used locally by the respective timer.
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Comparator Value Register.
The comparator value register yields a different behavior depending on the timer mode:
For single-shot timers, the interrupt is issued (if enabled) once, as soon as the global timer is equal to the configured value. When using 32-bit timers, an additional interrupt is issued when the global counter overflows.
For periodic timers, the mode of operation is as follows:
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protected |
Comparator FSB Interrupt Route Register.
