Bibliography on Memory Power Management
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[ACM04]
Raksit Ashok, Saurabh Chheda, and Csaba Andras Moritz.
Coupling compiler-enabled and conventional memory accessing for energy efficiency.
ACM Transactions on Computer Systems, 22(2):180–213, May 2004.
doi: 10.1145/986533.986535
[ bib | doi ]
[ACMM05]
Nevine AbouGhazaleh, Bruce Childers, Daniel Mosse, and Rami Melhem.
Near-memory caching for improved energy consumption.
In Proceedings of the 2005 International Conference on Computer Design (ICCD'05), October 2005.
doi: 10.1109/ICCD.2005.79
[ bib | doi ]
[AGS+02]
Ning An, Sudhanva Gurumurthi, Anand Sivasubramaniam, Narayanan Vijaykrishnan, Mahmut Kandemir, and Mary Jane Irwin.
Energy-performance trade-offs for spatial access methods on memory-resident data.
International Journal on Very Large Databases, 2002.
doi: 10.1007/s00778-002-0073-x
[ bib | doi ]
[Alb99]
David H. Albonesi.
An architectural and circuit-level approach to improving the energy efficiency of microprocessor memory structures.
In Proceedings of the 10th International Conference on VLSI, December 1999.
[ bib | .ps ]
[AN03]
T. Givargis A. Nacul.
Adaptive cache management for low power embedded systems.
Korea Multimedia Society, Key Technology of Next Generation IT, pages 30–39, December 2003.
[ bib | http ]
[Bel04]
Frank Bellosa.
When physical is not real enough.
In Proceedings of the Eleventh ACM SIGOPS European Workshop 2004, September 2004.
[ bib | .pdf ]
[BMP03]
Luca Benini, Alberto Macii, and Massimo Poncino.
Energy-aware design of embedded memories: A survey of technologies, architectures, and optimization techniques.
ACM Transactions on Embedded Computing Systems (TECS), 2(1), February 2003.
doi: 10.1145/605459.605461
[ bib | doi ]
[CC04]
Youngjin Cho and Naehyuck Chang.
Memory-aware energy-optimal frequency assignment for dynamic supply voltage scaling.
In Proceedings of the 2004 International Symposium on Low-Power Electronics and Design (ISLPED'04), pages 387–392, New York, NY, USA, August 2004. ACM Press.
doi: 10.1145/1013235.1013327
[ bib | doi ]
[CJDM99]
Vinodh Cuppu, Bruce Jacob, Brian Davis, and Trevor Mudge.
A performance comparison of contemporary DRAM architectures.
In Proceedings of the 26th International Symposium on Computer Architecture (ISCA'99), May 1999.
doi: 10.1145/300979.300998
[ bib | doi ]
[CSK+02]
G. Chen, R. Shetty, M. Kandemir, N. Vijaykrishnan, M. J. Irwin, and M. Wolczko.
Tuning garbage collection for reducing memory system energy in an embedded java environment.
ACM Transactions on Embedded Computing Systems (TECS), 1(1), November 2002.
doi: 10.1145/581888.581892
[ bib | doi ]
[DGJB07]
B. Diniz, D. Guedes, W. Meira Jr., and R. Bianchini.
Limiting the power consumption of main memory.
In Proceedings of the 34th International Symposium on Computer Architecture (ISCA'07), June 2007.
[ bib | .pdf ]
[DKK02]
Victor Delaluz, Mahmut T. Kandemir, and Ibrahim Kolev.
Automatic data migration for reducing energy consumption in multi-bank memory systems.
In Proceedings of the 39th Design Automation Conference (DAC'02), June 2002.
doi: 10.1145/513918.513973
[ bib | doi ]
[DKV+02]
V. Delaluz, M. Kandemir, N. Vijaykrishnan, M. J. Irwin, A. Sivasubramaniam, and I. Kolcu.
Compiler-directed array interleaving for reducing energy in multi-bank memories.
In Proceedings of the Seventh Asia and South Pacific Design Automation Conference and Fifteenth International Conference on VLSI Design (ASP-DAC'02 / VLSI Design'02), January 2002.
doi: 10.1109/ASPDAC.2002.994936
[ bib | doi ]
[DLK06]
Chia-Tien Da Lo and Mayumi Kato.
Power consumption reduction by memory compression in java embedded systems.
In Proceedings of the Twentieth Annual International Conference on Supercomputing (ICS'06), 2006.
[ bib | .pdf ]
[DLKB02]
Rajagopalan Desikan, Charles R. Lefurgy, Stephen W. Keckler, and Doug Burger.
On-chip MRAM as a high-bandwidth, low-latency replacement for DRAM physical memories.
Technical Report TR-02-47, Department of Computer Sciences, The University of Texas at Austin, September 2002.
[ bib | .pdf ]
[DSK+01]
V. Delaluz, A. Sivasubramaniam, M. Kandemir, N. Vijaykrishnan, and M. Irwin.
DRAM energy management using software and hardware directed power mode control.
In Proceedings of the Seventh International Symposium on High-Performance Computer Architecture (HPCA'01), January 2001.
[ bib | .html ]
[DSK+02]
V. Delaluz, A. Sivasubramaniam, M. Kandemir, N. Vijaykrishnan, and M. Irwin.
Scheduler based DRAM energy management.
In Proceedings of the 39th Design Automation Conference (DAC'02), June 2002.
doi: 10.1109/DAC.2002.1012714
[ bib | doi ]
[FEL01]
Xiaobo Fan, Carla Ellis, and Alvin Lebeck.
Memory controller policies for DRAM power management.
In Proceedings of the 2001 International Symposium on Low-Power Electronics and Design (ISLPED'01), August 2001.
[ bib | .pdf ]
[FEL02]
Xiaobo Fan, Carla S. Ellis, and Alvin R. Lebeck.
Synergy between power-aware memory systems and processor voltage scaling.
Technical Report CS-2002-12, Duke University, Department of Computer Science, November 2002.
[ bib | .pdf ]
[FEL03]
Xiaobo Fan, Carla Ellis, and Alvin Lebeck.
Interactions of power-aware memory systems and processor voltage scaling.
In Proceedings of the Workshop on Power-Aware Computer Systems (PACS'03), December 2003.
[ bib | .pdf ]
[GC09]
Fei Guo and Kit Colbert.
Understanding host and guest memory usage and other memory management concepts.
In VMworld 2009, 2009.
[ bib ]
[GDN01]
Peter Grun, Nikil Dutt, and Alex Nicolau.
Access pattern based local memory customization for low power embedded systems.
In Proceedings of the Conference on Design Automation and Test in Europe (DATE'01), pages 778–784, March 2001.
doi: 10.1109/DATE.2001.915120
[ bib | doi | http ]
[GDN03]
Peter Grun, Nikil Dutt, and Alex Nicolau.
Access pattern-based memory and connectivity architecture exploration.
ACM Transactions on Embedded Computing Systems (TECS), 2(1), February 2003.
doi: 10.1145/605459.605462
[ bib | doi ]
[HK01]
J. Hom and U. Kremer.
Energy management of virtual memory on diskless devices.
In Proceedings of the Workshop on Compilers and Operating Systems for Low Power (COLP'01), September 2001.
[ bib | .pdf ]
[HKM02]
Zhigang Hu, Stefanos Kaxiras, and Margaret Martonosi.
Timekeeping in the memory system: Predicting and optimizing memory behavior.
In Proceedings of the 29th International Symposium on Computer Architecture (ISCA'02), May 2002.
[ bib | .pdf ]
[HPS03]
H. Huang, P. Pillai, and K. G. Shin.
Design and implementation of power-aware virtual memory.
In Proceedings of the 2003 USENIX Annual Technical Conference, June 2003.
[ bib | .html ]
[Inc04a]
Micron Technology Inc.
240-Pin 256MB, 512MB, 1GB DDR2 SDRAM FBDIMM (SR, FB, x72) Features, 2004.
[ bib ]
[Inc04b]
Micron Technology Inc.
512Mb: x4, x8, x16 DDR2 SDRAM Features, 2004.
[ bib ]
[Inc05]
Micron Technology Inc.
Mobile DRAM power-saving features/calculations.
Technical Report TN-46-12, Micron Technology Inc., 2005.
[ bib ]
[Inc07]
Micron Technology Inc.
Calculating memory system power for DDR3.
Technical Report TN-41-01, Micron Technology Inc., 2007.
[ bib ]
[Jan01]
Jeff Janzen.
Calculating memory system power for DDR SDRAM.
Designline, 10(2), 2001.
[ bib | .pdf ]
[JCS+02]
Yongsoo Joo, Yongseok Choi, Hojun Shim, Hyung Lee, Kwanho Kim, and Naehyuck Chang.
Energy exploration and reduction of SDRAM memory systems.
In Proceedings of the 39th Design Automation Conference (DAC'02), June 2002.
doi: 10.1145/513918.514138
[ bib | doi ]
[JLN97]
Toni Juan, Thomas Lang, and Juan J. Navarro.
Reducing TLB power requirements.
In Proceedings of the 1997 International Symposium on Low Power Electronics and Design, pages 196–201, August 1997.
doi: 10.1145/263272.263332
[ bib | doi ]
[Joh01]
Chris Johnson.
BAT-RAM memory for battery-powered applications.
Designline, 10(1), 2001.
[ bib | .pdf ]
[KTFN02]
Masaaki Kondo, Shinichi Tanaka, Motonobu Fujita, and Hiroshi Nakamura.
Reducing memory system energy in data intensive computations by software-controlled on-chip memory.
In Proceedings of the Workshop on Compilers and Operating Systems for Low Power (COLP'02), September 2002.
[ bib | .pdf ]
[LB03]
Hsien-Hsin S. Lee and Chinnakrishnan S. Ballapuram.
Energy efficient D-TLB and data cache using semantic-aware multilateral partitioning.
In Proceedings of the 2003 International Symposium on Low-Power Electronics and Design (ISLPED'03), pages 306–311, August 2003.
[ bib | .pdf ]
[LFZE00]
Alvin Lebeck, Xiaobo Fan, Heng Zeng, and Carla Ellis.
Power aware page allocation.
In Proceedings of the Ninth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS'00), November 2000.
[ bib | .pdf ]
[LLD+04]
Xiaodong Li, Zhenmin Li, Francis M. David, Pin Zhou, Yuanyuan Zhou, Sarita V. Adve, and Sanjeev Kumar.
Performance directed energy management for main memory and disks.
In Proceedings of the Eleventh International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS'04), October 2004.
doi: 10.1145/1024393.1024425
[ bib | doi ]
[Mic05]
Micron Technology.
Calculating DDR Memory System Power, 2005.
Technical Note TN-46-03.
[ bib | .pdf ]
[Mic09]
Micron Technology.
Power-Saving Features of Mobile LPDRAM, 2009.
Technical Note TN-46-12.
[ bib | .pdf ]
[MMC00]
Afzal Malik, Bill Moyer, and Dan Cermak.
A low power unified cache architecture providing power and performance flexibility.
In Proceedings of the 2000 international symposium on Low power electronics and design, pages 241–243, July 2000.
[ bib | http ]
[MS99]
T. Martin and D. Siewiorek.
The impact of battery capacity and memory bandwidth on CPU speed-setting: a case study.
In Proceedings of the 1999 International Symposium on Low-Power Electronics and Design (ISLPED'99), August 1999.
[ bib | .pdf ]
[Mül09]
Sergej Müller.
Improving memory management with hardware-generated memory access profiles.
Study thesis, University of Karlsruhe, Germany, June 30 2009.
[ bib | .pdf ]
[PJZB06]
Vivek Pandey, Weihang Jiang, Yuanyuan Zhou, and Ricardo Bianchini.
DMA-aware memory energy conservation.
In Proceedings of the Twelfth International Symposium on High-Performance Computer Architecture (HPCA'06), February 2006.
[ bib | .pdf ]
[SD95]
Ching-Long Su and Alvin M. Despain.
Cache design trade-offs for power and performance optimization: a case study.
In Proceedings of the 1995 International Symposium on Low Power Design, pages 63–68, April 1995.
[ bib | http ]
[SDR02]
G.Edward Suh, Srinivas Devadas, and Larry Rudolph.
A new memory monitoring scheme for memory-aware scheduling and partitioning.
In Proceedings of the Eighth International Symposium on High-Performance Computer Architecture (HPCA'02), February 2002.
[ bib | .html ]
[SVD03]
Z. Stamenkovic, F. Vater, and Z. Dyka.
A framework for selection of cache configurations for low power.
In Proceedings of International Workshop on IP Based System-on-Chip Design, November 2003.
[ bib | .html ]
[Tre01]
R. B. Tremaine.
IBM memory expansion technology (MXT).
IBM Journal of Research and Development, 45(2):271–285, 2001.
doi: 10.1147/rd.452.0271
[ bib | doi ]
[TVK+01]
S. Tomar, N. Vijayakrishnan, M. Kandemir, A. Sivasubramaniam, and M. J. Irwin.
Energy behavior of java applications from the memory perspective.
In Proceedings of the Java Virtual Machine Research and Technology Symposium (JVM'01), April 2001.
[ bib ]
[UNS02]
Sumesh Udayakumaran, Bhagi Narahari, and Rahul Simha.
Application specific memory partitioning for low power.
In Proceedings of the Workshop on Compilers and Operating Systems for Low Power (COLP'02), September 2002.
[ bib | .pdf ]
[VHS98]
Joerg Vollrath, Markus Huebl, and Ernst Stahl.
Power analysis of DRAMs.
In Proceedings of the Seventh Asian Test Symposium, 1998.
doi: 10.1109/ATS.1998.741635
[ bib | doi ]
[Vog04]
P. Vogt.
Fully buffered DIMM (FB-DIMM) server memory architecture: Capacity, performance, reliability, and longevity.
In Intel Developer Forum, February 2004.
[ bib ]
[WKS99]
Paul R. Wilson, Scott F. Kaplan, and Yannis Smaragdakis.
The case for compressed caching in virtual memory systems.
In Proceedings of the USENIX 1999 Annual Technical Conference, pages 101–116, 1999.
[ bib | .pdf ]
[YDLC10]
Lei Yang, Robert P. Dick, Haris Lekatsas, and Srimat Chakradhar.
High-performance operating system controlled online memory compression.
ACM Transactions on Embedded Computing Systems (TECS), 9(4):1–28, 2010.
doi: 10.1145/1721695.1721696
[ bib | doi ]
