Class abstracting a single HPET comparator.
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#include <machine/hpet.h>
Class abstracting a single HPET comparator.
Abstracts the access to comparators. This class does not have any constructor, as it is used to encapsulate hardware structures already residing in memory.
The Registers for HPET comparator n are memory mapped at HPET base address plus offset
0x100 + 0x20 * n for Configuration and Capability Register0x108 + 0x20 * n for Comparator Value Register and0x110 + 0x20 * n for FSB Interrupt Route Register
Use HPET::getComparator to obtain an instance for a particular HPET comparator.
- See also
- IA-PC HPET - 2.3.8 Timer N Configuration and Capabilities Register
◆ HPET::Comparator::ConfigAndCapabilitiesRegister.__unnamed__
| struct HPET::Comparator::ConfigAndCapabilitiesRegister.__unnamed__ |
| Class Members |
|---|
|
uint64_t |
__pad0__: 1 |
|
|
TriggerMode |
trigger_mode: 1 |
Generate edge or level triggered interrupts. |
|
uint64_t |
interrupt_status: 1 |
Enable (1) or disable (0) interrupts. |
|
ComparatorMode |
comparator_mode: 1 |
periodic or one shot mode |
|
uint64_t |
periodic_capable: 1 |
Is timer capable of periodic mode (read-only) |
|
CounterSize |
counter_size: 1 |
32- or 64bit size (read-only) |
|
uint64_t |
set_value: 1 |
if set to 1, the accumulator can be set in software |
|
uint64_t |
__pad1__: 1 |
|
|
uint64_t |
small_mode: 1 |
if set to 1 while supporting 64bit size, the timer runs in 32-bit mode |
|
uint64_t |
ioapic_slot: 5 |
I/O-APIC slot (must be set in mask supported_ioapic_slots) |
|
uint64_t |
fsb_interrupt_enabled: 1 |
if set to 1, the timer will use FSB interrupt mapping |
|
uint64_t |
fsb_interrupt_delivery: 1 |
if set to 1, the timer supports FSB interrupt mapping (read-only) |
|
uint64_t |
__pad2__: 16 |
|
|
uint64_t |
supported_ioapic_slots: 32 |
bit mask containing the supported I/O APIC slots (read-only) |
◆ TriggerMode
Trigger mode for the interrupts generated by a comparator.
| Enumerator |
|---|
| EDGE | edge triggered
|
| LEVEL | level triggered
|
◆ ComparatorMode
Comparator mode a comparator is running in.
| Enumerator |
|---|
| ONE_SHOT | single shot (non-periodical)
|
| PERIODIC | periodical
|
◆ enable()
| void HPET::Comparator::enable |
( |
| ) |
|
|
inline |
Activates interrupts (for the current comparator).
- Optional:
- Implement Method
◆ disable()
| void HPET::Comparator::disable |
( |
| ) |
|
|
inline |
Deactivates interrupts (for the current comparator).
- Optional:
- Implement Method
◆ isEnabled()
| bool HPET::Comparator::isEnabled |
( |
| ) |
const |
|
inline |
Checks whether interrupts are enabled for the current comparator.
- Optional:
- Implement Method
◆ supportsIOAPICSlot()
| bool HPET::Comparator::supportsIOAPICSlot |
( |
unsigned |
slot | ) |
const |
|
inline |
Can this comparator trigger interrupts at an specific I/O-APIC Slot?
The standard mapping (not legacy or FSB!) is able to route interrupts to some I/O APIC slots. The possible slots can be determined by the corresponding bit in supported_ioapic_slots of the ConfigAndCapabilitiesRegister
- Note
- Currently Qemu/KVM only supports one slot (2) for comparators, which is shared as well.
- See also
- IA-PC HPET - 2.4.2.2 Mapping Option #2: Standard Option
- Parameters
-
| slot | I/O-APIC slot to check |
- Returns
true if comparator is capable to route interrupts to the given slot
- Optional:
- Implement Method
◆ supportsPeriodicInterrupts()
| bool HPET::Comparator::supportsPeriodicInterrupts |
( |
| ) |
const |
|
inline |
◆ isActive()
| bool HPET::Comparator::isActive |
( |
| ) |
const |
Check if this comparator triggered an interrupt.
Reads the corresponding bit of the General Interrupt Status Register if this comparator triggered an interrupt
- Note
- Only works for comparators operating in LEVEL triggered mode!
- See also
- IA-PC HPET - 2.3.6 General Interrupt Status Register
- Returns
- true if interrupt was triggered
- Optional:
- Implement Method
◆ setHandled()
| void HPET::Comparator::setHandled |
( |
| ) |
|
◆ set()
| bool HPET::Comparator::set |
( |
uint64_t |
usecs, |
|
|
uint8_t |
slot, |
|
|
bool |
periodic |
|
) |
| |
Sets the comperator.
Calculates the required ticks, sets the mode and I/O APIC slot for this comparator.
Since the I/O APIC slot might be shared with another device, the comparator should be configured to use level triggered interrupts (in standard interrupt mapping). The handler has to use isActive to verify that this HPET comparator was the source and mark it as handled.
- Note
- For periodic comperators, you need to reset the global counter to zero (using HPET::reset) to guarantee that the first interrupt will be fired (and therefore the comparator turns operational).
-
The global counter should be disabled while configuring the comparator (or you might lose interrupts)
- See also
- IA-PC HPET - 2.3.9.2.2 Periodic Mode
- Parameters
-
| usecs | time to wait in micro seconds. |
| slot | I/O APIC slot to be triggered on expiry of waiting time |
| periodic | If set, the interrupt will be issued periodically |
- Returns
true iff comperator was set up successful, false otherwise.
- Optional:
- Implement Method
◆ config_register
| volatile uint64_t HPET::Comparator::config_register |
|
protected |
Comparator Configuration and Capability Register.
In addition to global configuration and value registers, every HPET comparator comes with its own configuration register containing config used locally by the respective timer.
- Note
- Only 32- or 64-bit access allowed (use local temporary copy for modifications)
- See also
- IA-PC HPET - 2.3.8 Timer N Configuration and Capabilities Register
◆ value_register
| volatile uint64_t HPET::Comparator::value_register |
|
protected |
Comparator Value Register.
The comparator value register yields a different behavior depending on the timer mode:
For single-shot timers, the interrupt is issued (if enabled) once, as soon as the global timer is equal to the configured value. When using 32-bit timers, an additional interrupt is issued when the global counter overflows.
For periodic timers, the mode of operation is as follows:
- A first interrupt will be triggered when the global counter is equal to the value stored in this register.
- From there on, the HPET will automatically increase the value by the initial period. Reading from this registers will return the point in time the next interrupt will be issued.
- Note
- Only 32- or 64-bit access allowed
- See also
- IA-PC HPET - 2.3.10 Timer N FSB Interrupt Route Register
◆ fsb_register
| volatile uint64_t HPET::Comparator::fsb_register |
|
protected |
The documentation for this class was generated from the following files:
- machine/hpet.h
- machine/hpet.cc
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