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The Real-Time Systems Compiler

New:
RTSC Experimental Stage

Here, you can find the most recent results from our multi-core experiments.

The Real-Time Systems Compiler (RTSC) aims at providing an operating system aware compiler that allows for a generic manipulation of the real-time systems architecture of a given real-time application. Hereby, manipulating the real-time systems architecture makes possible many interesting applications like migrating event-triggered to time-triggered systems and vice versa.

Selected Publications

Software: Practice and Experience 2011

Scheler, Fabian ; Schröder-Preikschat, Wolfgang:
The Real-Time Systems Compiler: migrating event-triggered systems to time-triggered systems .
In: Software: Practice and Experience 41 (2011), No. 12, pp 1491-1515
Keywords:  Atomic Basic Blocks; ABB; RTSC; Real-Time Systems Compiler; Real-Time Systems; Echtzeitsysteme; Event-Triggered Systems; Time-Triggered Systems
[doi>10.1002/spe.1099] (BibTeX)

Real-Time Systems Architectures

A real-time systems architecture provides means to arrange and coordinate the different concurrent tasks forming a real-time application. These measures comprise the activation of event handlers in response to the occurrence of an event, scheduling and dispatching these tasks to shared CPU and various mechanisms for unilateral (e.g. messages) and multilateral (e.g. mutexes) synchronization. Usually, such real-time systems architectures are implemented by an RTOS. The OSEK OS and AUTOSAR OS, for instance, implement event-triggered real-time systems architectures, whereas the OSEK time-triggered OS implements a strictly time-triggered real-time systems architecture.

Manipulating the real-time systems architecture of a real-time application demands for a proper abstraction to hide all its specific details without losing the necessary information of the structure of the real-time application. So, the mapping between the event handlers and the corresponding triggering events must be preserved just as the temporal properties of those events and inter-task dependencies resulting from unilateral and multilateral synchronization.

Within the RTSC we use Atomic Basic Blocks and a System Model to implement such an abstraction. Essentially, the RTSC uses ABBs to derive a global dependency graph based on an inter-procedural control flow graph from a real-time application given as source code. This dependency graph is annotated with temporal information of the executed code (e.g. worst case execution time) and the triggering events. Technically, the RTSC is designed as an operating system aware compiler and it implemented on-top of the LLVM and we exploit the control flow model of the LLVM to implement ABBs. Thereby, it is possible to perform the necessary control flow based manipulations of the real-time systems architecture and the RTSC significantly benefits from the powerful LLVM framework when it comes to standard compiler analyses and optimizations.

Related Projects

The RTSC serves as the main research vehicle within the ABB and the AORTA research projects. In the ABB project we initially developed our first ideas towards generically manipulating the real-time systems architecture and came up with Atomic Basic Blocks to provide an appropriate intermediate representation for a tool like the RTSC. In the course of this project, we also created the first prototype of the RTSC. The follow-up project AORTA serves the purpose to further investigate the potential of ABBs.

Full Publications List

2014

Klaus, Tobias ; Franzmann, Florian ; Engelhard, Tobias ; Scheler, Fabian ; Schröder-Preikschat, Wolfgang: Usable RTOS-APIs? In: Brandenburg, Björn B. ; Kato, Shinpei (Hrsg.) : Proceedings of the 10th Annual Workshop on Operating Systems Platforms for Embedded Real-Time Applications (10th Workshop on Operating Systems Platforms for Embedded Real-Time Applications (OSPERT '14) Madrid 08.07.2014). Kaiserslautern, DE : Max Planck Institute for Software Systems, 2014, S. 61-66. (BibTeX)

2011

Scheler, Fabian: Atomic Basic Blocks: Eine Abstraktion für die gezielte Manipulation der Echtzeitsystemarchitektur . Erlangen, Friedrich-Alexander-Universität Erlangen-Nürnberg, Diss., 2011. - 171 Seiten. (BibTeX)

Scheler, Fabian ; Schröder-Preikschat, Wolfgang: The Real-Time Systems Compiler: migrating event-triggered systems to time-triggered systems . In: Software: Practice and Experience 41 (2011), Nr. 12, S. 1491-1515
[doi>10.1002/spe.1099] (BibTeX)

2010

Scheler, Fabian ; Schröder-Preikschat, Wolfgang: The RTSC: Leveraging the Migration from Event-Triggered to Time-Triggered Systems . In: Obermaisser, Roman (Hrsg.) : Proceedings of the 13th IEEE International Symposium on Object/Component/Service-oriented Real-time Distributed Computing (ISORC '10) (IEEE International Symposium on Object/Component/Service-oriented Real-time Distributed Computing Carmona May 2010). Washington : IEEE Press, 2010, S. 34-41. - ISBN 978-0-7695-4037-5
[doi>10.1109/ISORC.2010.11] (BibTeX)

2007

Scheler, Fabian ; Mitzlaff, Martin ; Schröder-Preikschat, Wolfgang: Atomic Basic Blocks . In: Holleczek, Peter ; Vogel-Heuser, Birgit (Hrsg.) : Mobilität und Echtzeit (PEARL 2007 Boppard 06./07.12.2007). 2007, S. 59-68. (Informatik aktuell) - ISBN 978-3-540-74836-6 (BibTeX)

Scheler, Fabian ; Mitzlaff, Martin ; Schröder-Preikschat, Wolfgang ; Schirmeier, Horst: Towards a Real-Time Systems Compiler . In: Seepold, Ralf ; Martinez Madrid, Natividad ; Kucera, Markus (Hrsg.) : Proceedings of the Fifth International Workshop on Intelligent Solutions in Embedded Systems (WISES 07) (Fifth International Workshop on Intelligent Solutions in Embedded Systems (WISES 07) Leganes (Madrid) 21./22.06.2007). Leganes (Madrid) : IEEE, 2007, S. 62-75. - ISBN 978-84-89315-47-1 (BibTeX)

2006

Scheler, Fabian ; Schröder-Preikschat, Wolfgang: Synthesising Real-Time Systems from Atomic Basic Blocks . In: IEEE Technical Committee on Real-Time Systems (Hrsg.) : Proceedings Work-In-Progress Session (12th Real-Time and Embedded Technology and Applications Symposium San Jose, USA 4-7 April, 2006). 2006, S. 49-52. (BibTeX)

People Involved in AORTA

Max Eschenbacher
Michael Höfler
Rebekka Rupprecht
Rolf Weber

Theses

Open Topics

A Deadlock-Resolving Resource Protocol for the RTSC (RESOURCE_RTSC)
Supervisors: Dipl.-Ing. Florian Franzmann, Dipl.-Ing. Tobias Klaus, Prof. Dr.-Ing. Wolfgang Schröder-Preikschat


LLVM in Time: Extending The Intermediate Language With ABB Support (AORTA_RTSC_NG)
Supervisors: Dipl.-Ing. Tobias Klaus, Dipl.-Ing. Florian Franzmann, Dr.-Ing. Peter Ulbrich


Portierung von TTEthernet auf phyCORE-TC1797 (AORTA_TTETHERNET)
Supervisors: Dipl.-Ing. Florian Franzmann, Dipl.-Ing. Tobias Klaus, Prof. Dr.-Ing. Wolfgang Schröder-Preikschat


Unstoppable: A Predictable Operating-System Executive (MA_POSE)
Supervisors: Prof. Dr.-Ing. Wolfgang Schröder-Preikschat, Gabor Drescher, M. Sc., Dr.-Ing. Peter Ulbrich


Werkzeuggestützte Überführung des I4Copters in ein verteiltes Echtzeitsystem (RTSC_I4COPTER)
Supervisors: Dipl.-Ing. Tobias Klaus, Dipl.-Ing. Florian Franzmann, Dr.-Ing. Peter Ulbrich

Ongoing Theses

Echtzeitgewahres Simulink (RTSC_SIMULINK)
Supervisors: Dipl.-Ing. Tobias Klaus, Dipl.-Ing. Florian Franzmann, Dr.-Ing. Peter Ulbrich, Prof. Dr.-Ing. Wolfgang Schröder-Preikschat


Entwurf und Implementierung einer Beschreibung für Mehrprozessor- und verteilte Systeme im RTSC (RTSC_ARCH)
Supervisors: Dipl.-Ing. Florian Franzmann, Dipl.-Ing. Tobias Klaus, Dr.-Ing. Peter Ulbrich, Prof. Dr.-Ing. Wolfgang Schröder-Preikschat

Finished Theses

Design and Implementation of a TriCore Backend for the LLVM Compiler Framework (ABB_LLVM_TRICORE)
Student: Christoph Erhardt (handed in on 01.09.2009, Thesis file...)
Supervisors: Prof. Dr.-Ing. Wolfgang Schröder-Preikschat, Dr.-Ing. Fabian Scheler


Entwurf und Implementierung eines POSIX-Back-End für den RTSC (AORTA_RTSC_ECOS_AUTOSAR)
Student: Tobias Klaus (handed in on 15.02.2013 )
Supervisors: Dr.-Ing. Fabian Scheler, Dipl.-Ing. Florian Franzmann, Prof. Dr.-Ing. Wolfgang Schröder-Preikschat


Statische Ablaufplanung von Abhängigkeitsgraphen ereignisgesteuerter Echtzeitsysteme (ABB_HAPPENSBEFORE_SCHED)
Student: Julian Exner (handed in on 31.03.2009 )
Supervisors: Prof. Dr.-Ing. Wolfgang Schröder-Preikschat, Dr.-Ing. Fabian Scheler


Statische WCET Analyse von LLVM Bytecode (ABB_LLVM_WCET_ANALYSIS)
Student: Benjamin Oechslein (handed in on 01.08.2008, Thesis file...)
Supervisors: Prof. Dr.-Ing. Wolfgang Schröder-Preikschat, Dr.-Ing. Fabian Scheler


Tool-based Selective Replication of Critical System-Components for SW-based Redundancy in Dependable Embedded Real-Time Systems (CoRed_RTSC_SWR)
Supervisors: Dr.-Ing. Fabian Scheler, Dr.-Ing. Peter Ulbrich, Prof. Dr.-Ing. Wolfgang Schröder-Preikschat


WCET-gewahre Optimierung im RTSC (AORTA_RTSC_WCET_COMPILER)
Supervisors: Dr.-Ing. Fabian Scheler