The Real-Time Systems Compiler
The Real-Time Systems Compiler (RTSC) aims at
providing an operating system aware compiler that allows for a generic
manipulation of the real-time systems architecture of a given real-time
application. Hereby, manipulating the real-time systems architecture makes
possible many interesting applications like migrating event-triggered to
time-triggered systems and vice versa.
- June 2013 - Peter Wägemann finished the
integration of the LLVM optimization strategy into the RTSC. Thereby, the RTSC
directly benefits from the LLVM's striking analyses and transformations. The
icing on the cake definitly is the semi-automatic check if
LLVM-transformations interfere with WCET-annotations as employed within the
RTSC. Check out his great work he presented in his concluding talk.
- May 2013 - Purnima Singhal from NIT -
Agartala (India) joined to RTSC-team for a three-month internship. During her
internship Purnima works on the integration of the Absint aiT WCET-Analyzer into the RTSC.
Do not issue a single analysis for each basic block anymore, as the
overhead of creating processes in Linux is fairly high. This will improve
the analysis-speed within the RTSC a lot.
Analyze larger chunks of code at once (e.g. complete function bodies)
instead of analyzing each basic block in isolation. The analysis will
thereby gain a lot more precision.
- November 2012 - Peter Wägemann joined the
RTSC-team to exploit more LLVM-provided optimizations inside the RTSC:
As the RTSC also contains an automated WCET analysis mechanism
optimizations like loop unrolling or loop un-switching are highly
problematic. Annotations about loop bounds have to be propagated properly,
the code finally emitted for the target must comply to the results of the
WCET analysis ...
Peter will classify problematic and non-problematic optimizations and
develop concept to consistently apply them throughout the compilation and
analysis process inside the RTSC. Currently, the RTSC makes use of only a
few LLVM-provided optimizations, so the RTSC will benefit a lot from his
- October 2012 - In the near future the RTSC
will receive some amazing new features:
Tobias Klaus currently works on an event-triggered back-end targeting
POSIX-based systems. So, the RTSC will enter the domain of
event-triggered target systems!
Florian Franzmann recently finished the support for preemptive
EDF-scheduling in the time-triggered back-end. The next step on the
road map is the support for multi-core scheduling!
Real-Time Systems Architectures
A real-time systems architecture provides means to arrange and coordinate
the different concurrent tasks forming a real-time application. These measures
comprise the activation of event handlers in response to the occurrence of an
event, scheduling and dispatching these tasks to shared CPU and various
mechanisms for unilateral (e.g. messages) and multilateral (e.g. mutexes)
synchronization. Usually, such real-time systems architectures are implemented
RTOS. The OSEK
OS, for instance, implement event-triggered real-time systems architectures,
whereas the OSEK
time-triggered OS implements a strictly time-triggered real-time systems
Manipulating the real-time systems architecture of a real-time application
demands for a proper abstraction to hide all its specific details without losing
the necessary information of the structure of the real-time application. So, the
mapping between the event handlers and the corresponding triggering events must
be preserved just as the temporal properties of those events and inter-task
dependencies resulting from unilateral and multilateral synchronization.
Within the RTSC we use Atomic Basic
Blocks and a System Model to
implement such an abstraction. Essentially, the RTSC uses ABBs to derive a
global dependency graph based on an inter-procedural control flow graph from a
real-time application given as source code. This dependency graph is annotated
with temporal information of the executed code (e.g. worst case execution time)
and the triggering events. Technically, the RTSC is designed as an operating
system aware compiler and it implemented on-top of
the LLVM and we exploit the control flow model
of the LLVM to implement ABBs. Thereby, it is possible to perform the necessary
control flow based manipulations of the real-time systems architecture and the
RTSC significantly benefits from the powerful LLVM framework when it comes to
standard compiler analyses and optimizations.
The RTSC serves as the main research vehicle within the ABB and the AORTA
research projects. In the ABB project we initially developed our first ideas
towards generically manipulating the real-time systems architecture and came up
with Atomic Basic Blocks to provide an appropriate intermediate
representation for a tool like the RTSC. In the course of this project, we also
created the first prototype of the RTSC. The follow-up project AORTA serves the
purpose to further investigate the potential of ABBs.
If you are interested in the RTSC, Atomic Basic
Blocks or AORTA, do not hesitate to get in
touch with Fabian Scheler either via eMail, phone or